Read-only memory cell arrangement

ABSTRACT

A read-only memory cell arrangement having planar MOS transistors which are arranged in parallel rows. Neighboring rows run alternately on the bottom of longitudinal trenches and run between neighboring longitudinal trenches. Bit lines run transversely and word lines run parallel to the longitudinal trenches. The memory cell arrangement can be produced with an area per memory cell of 2F 2  (F-minimum structure size).

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor-based read-only memorycell arrangement which can be produced with both a small number ofproduction steps and a high yield and which exhibits increased storagedensity.

2. Description of the Prior Art

Memories to which data are written permanently are required for manyelectronic systems. Such memories are referred to, inter alia, asread-only memories.

Plastic disks coated with aluminum are in wide-spread use as read-onlymemories for very large volumes of data. These plastic disks have twodifferent kinds of point-like depressions in coating which arerespectively assigned to the logic values zero and one. The informationis stored digitally in the arrangement of these depressions. Such disksare referred to as compact disks and are widely used for the digitalstorage of music.

In order to read the data which are stored on a compact disk, the diskis rotated mechanically using a reading apparatus. The point-likedepressions are scanned by means of a laser diode and a photocell.Typical scanning rates in this case are 2×40 kHz. 5 Gbits of informationcan be stored on one compact disk.

The reading apparatus has moving parts which are subjected to mechanicalwear, require a comparatively large volume and allow only slow dataaccess. The reading apparatus is furthermore sensitive to vibrations andcan thus be used only to a limited extent in mobile systems.Semiconductor-based read-only memories are known for the storage ofsmaller volumes of data. These memories are often formed as a planarintegrated silicon circuit in which MOS transistors are used. The MOStransistors are respectively selected via the gate electrode connectedto the word line. The input of the MOS transistor is connected to areference line while the output is connected to a bit line. Anassessment is carried out during the reading operation to determinewhether or not a current is flowing through the transistor. The storedinformation is assigned accordingly. In technical terms, the storage ofthe information is usually effected by the MOS transistors havingdifferent threshold voltages as a result of different implantation inthe channel region.

These semiconductor-based memories allow random access to storedinformation. The electrical power required to read the information isdistinctly less than in a reading apparatus having a mechanical drive.Since a mechanical drive is not required to read the information, themechanical wear and the sensitivity to vibrations are obviated.Semiconductor-based read-only memories can therefore be used for mobilesystems as well.

In order to increase the storage density in planar silicon memories, ithas been proposed to arrange the MOS transistors in rows. In each row,the MOS transistors are connected in series. The MOS transistors areread out by row-by-row driving in the sense of a NAND or NORarchitecture. This requires only two terminals per row wherein the MOStransistors arranged in the row are connected in series between theterminals. Source/drain regions, connected to one another, ofneighboring MOS transistors can then be formed as a coherent dopedregion. This enables the area requirement per memory cell to be reducedto a theoretical value of 4F² (F-smallest structure size that can beproduced using the respective technology). Such a memory cellarrangement is disclosed, for example, in H. Kawagoe and N. Tsuji, IEEEJ. Solid-State Circ., vol. SC-11, P. 360 (1976).

SUMMARY OF THE INVENTION

The present invention is directed to a semiconductor-based read-onlymemory cell arrangement in which an increased storage density isachieved and which can be produced with both a small number ofproduction steps and a high yield. The present invention is furtherdirected to a method for producing such a memory cell arrangement.

The read-only memory cell arrangement of the present invention includesa multiplicity of individual memory cells in a semiconductor substratewhich is preferably made of monocrystalline silicon. The memory cellseach include at least one MOS transistor. The memory cells are eacharranged in rows which are substantially parallel. Longitudinaltrenches, which run substantially parallel to the rows, are provided ina main area of the semiconductor substrate. The rows are alternatelyarranged on the main area between neighboring longitudinal trenches andon the bottom of the longitudinal trenches. Bit lines run transverselywith respect to the rows and are each connected to source/drain regionsof MOS transistors arranged along different rows. Word lines arearranged above the rows and are each connected to the gate electrodes ofMOS transistors arranged along a row.

In order to prevent conductive channels being formed between neighboringrows in the semiconductor substrate, it is advantageous to provide dopedlayers in the semiconductor substrate between neighboring longitudinaltrenches. Such doped layers act as a channel stopper.

The read-only memory cell arrangement can be formed with an arearequirement per memory cell of 2F² (F-minimum structure size in therespective technology). For this purpose, the MOS transistors of memorycells arranged along a row are connected in series. Source/drainregions, connected to one another, of neighboring MOS transistors alonga row are correspondingly designed as a coherent doped region in thesemiconductor substrate. Source/drain regions which are connected alonga bit line, or transversely with respect to the longitudinal trenches,are connected to one another via doped regions in the semiconductorsubstrate. The doped regions are arranged in each of the side walls ofthe longitudinal trenches. In such an embodiment, the bit lines arerespectively formed by both the source/drain regions and the dopedregions in the side walls of the longitudinal trenches.

If the longitudinal trenches are formed with a trench width of F and ata distance F, and if the extend of the coherent doped regionsrespectively acting as source/drain regions, connected to one another,of two MOS transistors amounts to F, and if the extent of the channelregion amounts to F, then the resulting space requirement per memorycell is 2F² because each of the coherent doped regions belongs to twoneighboring memory cells and because neighboring rows of memory cellsare arranged directly next to one another. Insulation betweenneighboring rows of memory cells is ensured by the arrangement on thebottom of the longitudinal trench and on the main area of thesemiconductor substrate between neighboring longitudinal trenches.

It lies within the scope of the present invention that the MOStransistors have different threshold voltages depending on theinformation stored in the respective memory cell. In order to store datain a digital form, the MOS transistors have two different thresholdvoltages. If the read-only memory cell arrangement is to be used formultivalue logic, then the MOS transistors have more than two differentthreshold voltages depending on the stored information. It also lieswithin the scope of the present invention to realize different thresholdvoltages of the MOS transistors through different channel dopings of theMOS transistors.

According to one embodiment of the present invention, the MOStransistors have a dielectric multilayer coating as gate dielectric. Thedielectric multilayer coating is provided with at lest one layer whichhas an increased electron capture cross-section compared with at lestone further layer in the multilayer coating. The dielectric multilayercoating preferably includes an SiO₂ layer, an Si₃ N₄ layer and an SiO₂layer (so-called ONO). This embodiment of the read-only memory cellarrangement is one-time programmable by injecting electrons from thechannel region of the MOS transistors into the multilayer coating. Theinjected electrons are retained by traps in the depletion layer betweenSiO₂ and Si₃ N₄ and increase the threshold voltage of the MOStransistor. In this way, the threshold voltage of the respective MOStransistor is varied in a targeted manner depending on the informationto be stored in the respective memory cell.

The read-only memory cell arrangement is preferably produced usingself-aligning process steps wherein the space requirement per memorycell can be reduced. In order to produce the read-only memory cellarrangement, longitudinal trenches running substantially parallel areetched in a main area of a semiconductor substrate. A multiplicity ofmemory cells which are arranged in rows, and which each include at leastone MOS transistor, are produced wherein the rows are arrangedalternately on the main area between neighboring longitudinal trenchesand on the bottom of the longitudinal trenches. The source/drain regionsof the MOS transistors are produced by implantation wherein asource/drain mask is used which defines the arrangement of thesource/drain regions of the memory cells. Using the source/drain mask asan implantation mask, doped regions are subsequently formed by angledimplantation in the side walls of the longitudinal trenches. Such dopedregions connect together source/drain regions arranged along differentrows. Word lines, which are each connected to the gate electrodes of MOStransistors arranged along a row, are produced above the rows. Thesource/drain regions which are connected to one another via dopedregions in the side walls of the longitudinal trenches, and which arearranged along different rows, form bit lines in the read-only memorycell arrangement.

In order to suppress the formation of conductive channels in thesemiconductor substrate between neighboring rows it is advantageous toproduce a doped layer prior to the formation of the longitudinaltrenches in the semiconductor substrate. Such doped layer is etchedthrough during the etching of the longitudinal trenches and acts as achannel stopper in the read-only memory cell arrangement.

Additional features and advantages of the present invention aredescribed in, and will be apparent from, the Detailed Description of thePreferred Embodiments and from the Drawings.

DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a silicon substrate after a first channel implantation.

FIG. 2 shows the silicon substrate of FIG. 1 after trench etching and asecond channel implantation.

FIG. 3 shows a plan view of the silicon substrate of FIG. 2 with asource/drain mask after an implantation for the purpose of forming thesource/drain regions, and an angled implantation for the purpose offorming doped regions in the side walls of the longitudinal trenches.

FIG. 4 shows the section through the silicon substrate which isdesignated by IV--IV in FIG. 3.

FIG. 5 shows the section through the silicon substrate which isdesignated by V--V in FIG. 3.

FIG. 6 shows a section through the silicon substrate of FIG. 3 after theformation of a gate dielectric and the deposition of both a conductivelayer and an Si₃ N₄ layer.

FIG. 7 shows a section through the silicon substrate of FIG. 6 after theformation of Si₃ N₄ spacers and an oxide mask for structuring theconductive layer.

FIG. 8 shows a section through the silicon substrate of FIG. 7 after theformation of word lines by structuring of the conductive layer.

FIG. 9 shows the section designated by IX--IX in FIG. 8.

FIG. 10 shows the section designated by X--X in FIG. 8.

FIG. 11 shows a circuit diagram of the read-only memory cellarrangement.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In order to produce a read-only memory cell arrangement in a substrate 1made of, for example, monocrystalline silicon an insulation structurewhich defines the region of the read-only memory cell arrangement (notillustrated) and and which may define active regions for a peripheralarea of the read-only memory cell arrangement is produced on a main area2 of the substrate 1. The insulation structure is formed, for example,in a LOCOS process or in a shallow trench insulation process. Thesubstrate 1 is, for example, p-doped with a dopant concentration of5×10¹⁵ cm⁻³.

Implantation with boron is subsequently carried out in order to form achannel stop layer 3. The boron implantation is carried out with, forexample, a dose of 6×10¹³ cm⁻² and an energy of 120 keV. As a result,the channel stop layer 3 is produced at a depth of 0.3 μm, for example,below the main area 2 with a thickness of 0.3 μm (see FIG. 1).

A photolithographic process is then used to define regions for thedepletion channels of MOS transistors. The depletion channels 4 areformed with the aid of a first channel implantation using arsenic withan energy of 50 keV and a dose of 4×10¹³ cm⁻², for example. The extentof the depletion channels 4 parallel to the main area 2 is 0.6 μm×0.6μm, for example, if a 0.4 μm technology is used.

By depositing an SiO₂ layer to a thickness of 200 nm, for example, withthe aid of a TEOS process, a trench mask 5 is formed by structuring theSiO₂ layer with the aid of photolithographic processes (see FIG. 2).

Longitudinal trenches 6 are etched by anisotropic etching with Cl₂, forexample, using the trench mask 5 as an etching mask. The longitudinaltrenches 6 have a depth of 0.6 μm, for example. The longitudinaltrenches 6 reach down into the substrate 1 and cut through the channelstop layer 3. The width of the depletion channels 4 is set during theetching of the longitudinal trenches 6. For this reason, the alignmentof the trench mask 5 relative to the depletion channels 4 is notcritical.

Spacers 7 made of SiO₂ are formed on the side walls of the longitudinaltrenches 6 by depositing a further SiO₂ layer using a TEOS process andsubsequent anisotropic etching. A photolithographic process issubsequently used to define regions for the depletion channels for MOStransistors which are subsequently produced on the bottom of thelongitudinal trenches 6. Depletion channels 8 are produced on the bottomof the longitudinal trenches 6 by means of a second channel implantationwith, for example, arsenic and an energy of 50 keV and a dose of 4×10¹³cm⁻². The regions between neighboring longitudinal trenches 6 are maskedin the process by the trench mask 5 and the spacers 7. Therefore,alignment during the definition of the depletion channels 8 is notcritical. The second channel implantation is self-aligned with regard tothe side walls of the longitudinal trenches 6.

The trench mask 5 is subsequently removed wet-chemically using NH₄ F/HF,for example. The spacers 7 are removed at the same time.

A thin SiO₂ layer 9 is grown to a thickness of 20 nm, for example, onthe silicon surface. The thin SiO₂ layer 9 improves the silicon surfacein the sense of a sacrificial oxide.

A polysilicon layer is subsequently deposited over the whole area. Thepolysilicon layer is produced with a thickness of 500 nm, for exampleand is intrinsically doped. With the aid of photolithographic processsteps, a source/drain mask 10 is formed by structuring the polysiliconlayer (see FIG. 3, FIG. 4, FIG. 5). The source/drain mask 10 defines thearrangement of source/drain regions to be produced afterwards. Thesource/drain mask 10 has polysilicon strips which cover the siliconsurface in each of the regions in which channel regions for MOStransistors are subsequently produced.

By implanting arsenic with an energy of approximately 80 keV and a doseof approximately 5×10¹⁵ cm⁻², upper source/drain regions 11a arerespectively formed in the region of the main area 2 between neighboringlongitudinal trenches 6 and lower source/drain regions 11b arerespectively formed on the bottom of the longitudinal trenches 6. Theimplantation is carried out substantially perpendicularly with respectto the main area 2 (see FIG. 3 and FIG. 5).

Doped regions 12 are formed in the side walls of the longitudinaltrenches 6 by ion implantation with an angle of inclination of 40°, forexample, such doped regions respectively connect an upper source/drainregion 11a to a lower source/drain region 11b (see FIG. 5). The angledimplantation is carried out, for example, using arsenic with an energyof 5×10¹⁵ cm⁻² and a dose of 5×10¹⁵ cm⁻².

The source/drain mask 10 is subsequently removed by dry or wet etchingwhich attacks polysilicon selectively with respect to SiO₂. Accordingly,the thin SiO₂ layer 9 acts as an etching stop. The source/drain mask 10is removed, for example, by wet etching using polysilicon etchant(HF/HNO₃ /H₂ O) or by dry etching using HBr and Cl₂.

The thin SiO₂ layer 9 is subsequently removed using hydrofluoric acid(HF), for example.

SiO₂ spacers 13 are formed on the side walls of the longitudinaltrenches 6 by deposition of an SiO₂ layer in a TEOS process andsubsequent anisotropic etching (see FIG. 6).

A gate dielectric 14 made of SiO₂, for example, is formed to a thicknessof 10 nm, for example, by thermal oxidation. An oxidation conductivelayer 15 is subsequently produced over the whole area to a thickness ofapproximately 100 to 200 nm. The oxidizable conductive layer 15 ispreferably formed from doped polysilicon. As an alternative, theoxidizable conductive layer 15 may be formed of a metal silicide or acombination of doped polysilicon and silicide.

An Si₃ N₄ layer 16 is deposited over the whole area to a thickness of 30to 80 nm, for example. Planar parts of the Si₃ N₄ layer 16 are removedby anisotropic etching and Si₃ N₄ spacers 17 are formed. In the process,the surface of the oxidizable conductive layer 15 is uncovered in planarregions. The Si₃ N₄ spacers 17 cover the oxidizable conductive layer 15in the region of the side walls of the longitudinal trenches 6 (see FIG.7).

Uncovered regions of the oxidizable conductive layer 15 are subsequentlyoxidized. The Si₃ N₄ spacers 17 act as an oxidation mask and allowselective oxidation in the planar regions of the oxidizable conductivelayer 15. In the process, an oxide mask 18 is formed which covers theplanar regions of the oxidizable conductive layer 15.

The Si₃ N₄ spacers 17 are subsequently removed. The oxidizableconductive layer 15 is structures in an etching process which attacksthe oxidizable conductive layer 15 selectively with respect to the oxidemask 18. Word lines 19 running parallel to the longitudinal trenches 6are produced in the process on the bottom of the longitudinal trenches 6and also between neighboring longitudinal trenches 6 (see FIG. 8, FIG. 9and FIG. 10). The selective oxidation for forming the oxide mask 18makes it possible to structure the word lines 19 in a self-alignedmanner with respect to the course of the longitudinal trenches 6. Thewidth of such word lines 19 is less than the minimum structure sizeF-particularly on the bottom of the longitudinal trenches 6.

The read-only memory cell arrangement is wired up in a NOR configuration(see FIG. 11). This circuit architecture enables access to eachindividual memory cell within short time constants. In FIG. 11, the wordlines are designated by WL and the bit lines by BL.

The read-only memory cell arrangement is completed by deposition of anintermediate oxide. Contact holes are subsequently etched wherein theside walls of the contact holes are provided with insulating spacers andwherein the contact holes are filled with tungsten, for example.Finally, a metallization plane is produced by depositing a metal layerand structuring the metal layer (not illustrated).

The gate dielectric 14 may alternatively be formed from a layer sequenceSiO₂, Si₃ N₄ and SiO₂ (ONO). As such, the read-only memory cellarrangement is one-time programmable by electron injection from thechannel region of the MOS transistors into the gate dielectric.Electrons captured in the gate dielectric increase the threshold voltageof the MOS transistor. Accordingly, the two channel implantations forsetting different threshold voltages are omitted.

A suitable choice of the voltage conditions during the injection ofelectrons makes it possible to set different threshold voltages in orderto represent a plurality of logic values.

Although the present invention has been described with reference tospecific embodiments, those of skill in the art will recognize thatchanges may be made thereto without departing from the spirit and scopeof the invention as set forth in the hereafter appended claims.

What is claimed is:
 1. A read-only memory cell arrangement, comprising:asemiconductor substrate; a plurality of longitudinal trenches formed ina main area of the semiconductor substrate, the plurality oflongitudinal trenches being substantially parallel to each other; aplurality of individual memory cells formed in the semiconductorsubstrate, the plurality of individual memory cells arranged in rowswhich run substantially parallel to the plurality of longitudinaltrenches and which are alternately positioned on the main area betweenadjacent longitudinal trenches and on respective bottoms of thelongitudinal trenches, each of the plurality of individual memory cellsincluding at least one MOS transistor; a plurality of bit lines runningtransversely to the rows, each of the plurality of bit lines connectedto source/drain regions of MOS transistors respectively arranged alongdifferent rows; and a plurality of word lines positioned above the rows,each of the plurality of word lines connected to gate electrodes of MOStransistors arranged along a single row.
 2. A read-only memory cellarrangement as claimed in claim 1, further comprising:a plurality ofdoped layers formed in the semiconductor substrate, each of theplurality of doped layers positioned between adjacent longitudinaltrenches wherein conductive channels are prevented from forming betweenadjacent rows.
 3. A read-only memory cell arrangement as claimed inclaim 1, wherein:the MOS transistors of memory cells arranged along asingle row are connected in series; source/drain regions of adjacent MOStransistors arranged along a single row are designed as a coherent dopedregion in the semiconductor substrate; and the source/drain regionsconnected to a bit line and arranged along different rows are connectedto one another via doped regions on side walls of the plurality oflongitudinal trenches.
 4. A read-only memory cell arrangement as claimedin claim 1, wherein each MOS transistor has a respective thresholdvoltage dependent upon information stored in the MOS transistor'srespective memory cell.
 5. A read-only memory cell arrangement asclaimed in claim 1, wherein each MOS transistor further includes adielectric multilayer coating having at least one layer with anincreased electron capture cross-section compared to at least onefurther layer.
 6. A read-only memory cell arrangement as claimed inclaim 5, wherein the multilayer coating includes at least one SiO₂ layerand at least one Si₃ N₄ layer.